`timescale 1ns/1ps
`include "uvm_macros.svh"
import uvm_pkg::*;
`include "my_driver.sv"

module top_tb;
    reg clk;
    reg rst_n;
    reg [7:0] rxd;
    reg rx_dv;
    wire [7:0] txd;
    wire tx_en;

    my_if input_if(clk,rst_n);
    my_if output_if(clk,rst_n);

    dut my_dut(
        .clk(clk),
        .rxd(input_if.data),
        .rx_dv(input_if.valid),
        .txd(output_if.data),
        .tx_en(output_if.valid)
    );

    initial begin
        uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.drv","vif",input_if);
        uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.mon","vif",input_if);
        uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.o_agt.mon","vif",output_if);
    end
        

    initial begin
        run_test("base_test");
        //my_driver drv;
        //drv = new("drv",null);
        //drv.main_phase(null);
        //$finish;
    end

    initial begin
        clk=1'b0;
        forever #100 clk=~clk;
    end

    initial begin
        rst_n=1'b0;
        #100 rst_n=1'b1;
    end

endmodule
